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सीपीयू शिल्पों की तुलना

कम्प्यूटर शिल्प (Computer architecture) को प्रायः 8, 16, 32, or 64 बिट आदि के द्वारा समझा जाता है। किन्तु कम्प्यूटर शिल्प में इसके अलावा भी कुछ अन्य डेटा-साइज होते हैं।

शिल्प (Architectures)

नीचे की सारणी में सीपीयू शिल्प से सम्बन्धित मूलभूत सूचनाओं की ही तुलना की गैइ है।

शिल्प बिट संख्या संस्करण कब आया Max # Operandsटाइप डिजाइन रजिस्टरइंस्ट्रक्शन इन्कोडिंग ब्रांच इवैलुएशन EndiannessExtensions मुक्त रॉयल्टी-मुक्त
Alpha64 1992 3 Register-Register RISC32 Fixed Condition register Bi MVI, BWX, FIX, CIXनहीं Unknown
ARM32 ARMv7 and earlier 1983 3 Register-Register RISC 16 Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit)Condition code Bi NEON, Jazelle, VFP, TrustZone, LPAEUnknown नहीं
ARM64 ARMv8[1]2011[2]3 Register-Register RISC 30 Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit), A64 Condition code Bi NEON, Jazelle, VFP, TrustZoneUnknown नहीं
AVR3232 Rev 2 2006 2-3 RISC 15 Variable[3]Big Java Virtual MachineUnknown Unknown
Blackfin32 2000 RISC[4]8 Little[5]Unknown Unknown
DLX32 1990 3 RISC 32 Fixed (32-bit)Big Unknown Unknown
eSi-RISC16/32 2009 3 Register-Register RISC 8-72 Variable(16 or 32-bit)Compare and branch and condition register Bi User-defined instructions नहीं नहीं
Itanium (IA-64) 64 2001 Register-Register EPIC128 Condition register Bi (selectable) Intel Virtualization Technology हाँ हाँ
M32R32 1997 RISC 16 Fixed (16- or 32-bit)Bi Unknown Unknown
m68k16/32 1979 CISC16 Big Unknown Unknown
Mico3232 2006 3 Register-Register RISC 32[6]Fixed (32-bit)Compare and branch Big User-defined instructions हाँ[7]हाँ
MIPS64 (32→64)5 1981 3 Register-Register RISC 32 Fixed (32-bit)Condition register Bi MDMX, MIPS-3DUnknown नहीं
MMIX64 1999 3 Register-Register RISC 256 Fixed (32-bit)Big हाँ हाँ
PA-RISC (HP/PA) 64 (32→64)2.0 1986 3 RISC 32 Fixed Compare and branch Big Multimedia Acceleration eXtensions (MAX), MAX-2 नहीं Unknown
PowerPC32/64 (32→64)2.06[8]1991 3 Register-Register RISC 32 Fixed, Variable Condition code Big/Bi AltiVec, APU, VSX, Cellहाँ[9]नहीं
S+core16/32 2005 RISC Little Unknown Unknown
Series 3200032 1982 5 Memory-Memory CISC 8 Variable Huffman coded, up to 23 bytes long Condition Code Little BitBlt instructions Unknown Unknown
SPARC64 (32→64)V9 1985 3 Register-Register RISC 31 (of at least 55) Fixed Condition code Big → Bi VIS 1.0, 2.0, 3.0 हाँ हाँ[10]
SuperH (SH) 32 1990s 2 Register-Register/ Register-Memory RISC 16 Fixed Condition Code (Single Bit) Bi Unknown Unknown
System/360 / System/370 / z/Architecture64 (32→64)3 1964 Register-Memory/Memory-Memory CISC 16 Fixed Condition code Big Unknown Unknown
VAX32 1977 6 Memory-Memory CISC 16 Variable Compare and branch Little VAX Vector Architecture Unknown Unknown
x8632 (16→32)1978 2 Register-Memory CISC 8 Variable Condition code Little MMX, 3DNow!, SSE, PAE, नहीं नहीं
x86-6464 2003 2 Register-Memory CISC 16 Variable Condition code Little MMX, 3DNow!, PAE, AVXनहीं नहीं

सूक्ष्मशिल्प (Microarchitectures)

नीचे की सारणी में प्रमुख सूक्ष्मशिल्पों की तुलना की गई है।

Microarchitecture Pipeline stages Misc
AMD K5Out-of-order execution, register renaming, speculative execution
AMD K6Superscalar, branch prediction
AMD K6-IIIBranch prediction, speculative execution, out-of-order execution[11]
AMD K7Out-of-order execution, branch prediction, Harvard architecture
AMD K864-bit, integrated memory controller, 16 byte instruction prefetching
AMD K10Superscalar, out-of-order execution, 32-way set associative L3 victim cache, 32-byte instruction prefetching
ARM7TDMI(-S)3
ARM7EJ-S5
ARM810 5
ARM9TDMI5
ARM1020E 6
XScale PXA210/PXA2507
ARM1136J(F)-S8
ARM1156T2(F)-S9
ARM Cortex-A5 8
ARM Cortex-A813
ARM Cortex-A9Out-of-order, speculative issue, superscalar
ARM Cortex-A15Multicore (up to 16)
AVR32 AP77
AVR32 UC33 Harvard architecture
BobcatOut-of-order execution
BulldozerShared L3 cache, multithreading, multicore, integrated memory controller
CrusoeIn-order execution, 128-bit VLIW, integrated memory controller
EfficeonIn-order execution, 256-bit VLIW, fully integrated memory controller
Cyrix Cx5x866[12]Branch prediction
Cyrix 6x86Superscalar, superpipelined, register renaming, speculative execution, out-of-order execution
DLX5
eSi-32005 In-order, speculative issue
eSi-32505 In-order, speculative issue
EV4 (Alpha 21064)Superscalar
EV7 (Alpha 21364)Superscalar design with out-of-order execution, branch prediction, 4-way SMT, integrated memory controller
EV8 (Alpha 21464)Superscalar design with out-of-order execution
P5 (Pentium) 5 Superscalar
P6 (Pentium Pro) 14 Speculative execution, Register renaming, superscalar design with out-of-order execution
P6 (Pentium II) Branch prediction
P6 (Pentium III) 10
Itanium8[13]Speculative execution, branch prediction, register renaming, 30 execution units, multithreading
NetBurst (Willamette) 20 Simultaneous multithreading
NetBurst (Northwood) 20 Simultaneous multithreading
NetBurst (Prescott) 31 Simultaneous multithreading
NetBurst (Cedar Mill) 31 Simultaneous multithreading
Core14
Intel Atom16 Simultaneous multithreading, in-order. No instruction reordering, speculative execution, or register renaming.
NehalemSimultaneous multithreading, integrated memory controller, L1/L2/L3 cache
Sandy BridgeSimultaneous multithreading, multicore, integrated memory controller, L1/L2/L3 cache. 2 threads per core.
Haswell14 Multicore
LatticeMico326 Harvard architecture
POWER1Superscalar, out-of-order execution
POWER3Superscalar, out-of-order execution
POWER4Superscalar, speculative execution, out-of-order execution
POWER5Simultaneous multithreading, out-of-order execution, integrated memory controller
POWER62-way simultaneous multithreading, in-order execution
POWER74 SMT threads per core, 12 execution units per core
PowerPC 4013
PowerPC 4055
PowerPC 4407
PowerPC 4709 SMP
PowerPC A215
PowerPC e3004 Superscalar, Branch prediction
PowerPC e500Dual 7 stage Multicore
PowerPC e6003-issue 7 stage Superscalar out-of-order execution, branch prediction
PowerPC e55004-issue 7 stage Out-of-order, multicore
PowerPC 6034 5 execution units, branch prediction. No SMP.
PowerPC 603q5 In-order
PowerPC 6046 Superscalar, out-of-order execution, 6 execution units. SMP support.
PowerPC 6205 Out-of-order execution- SMP support.
PWRficientSuperscalar, out-of-order execution, 6 execution units
R40008 Scalar
StrongARM SA-1105 Scalar, in-order
SuperH SH25
SuperH SH2A5 Superscalar, Harvard architecture
SPARCSuperscalar
HyperSPARCSuperscalar
SuperSPARCSuperscalar, in-order
SPARC64 VI/VII/VII+ Superscalar, out-of-order[14]
UltraSPARC9
UltraSPARC T16 Open source, multithreading, multi-core, 4 threads per core, integrated memory controller
UltraSPARC T28 Open source, multithreading, multi-core, 8 threads per core
SPARC T38 Multithreading, multi-core, 8 threads per core, SMP
SPARC T416 Multithreading, multi-core, 8 threads per core, SMP, out-of-order
VIA C7In-order execution
VIA Nano (Isaiah) Superscalar out-of-order execution, branch prediction, 7 execution units
WinChip4 In-order execution

इन्हें भी देखें

सन्दर्भ

  1. ↑ "ARMv8 Technology Preview" (PDF). मूल (PDF) से 10 जून 2018 को पुरालेखित. अभिगमन तिथि 21 सितंबर 2012.
  2. ↑ "ARM goes 64-bit with new ARMv8 chip architecture". मूल से 3 मार्च 2012 को पुरालेखित. अभिगमन तिथि 26 मई 2012.
  3. ↑ "AVR32 Architecture Document" (PDF). Atmel. मूल (PDF) से 18 मार्च 2012 को पुरालेखित. अभिगमन तिथि 2008-06-15.
  4. ↑ "Blackfin Processor Architecture Overview". Analog Devices. मूल से 22 मई 2009 को पुरालेखित. अभिगमन तिथि 2009-05-10.
  5. ↑ "Blackfin memory architecture". Analog Devices. मूल से 16 जून 2011 को पुरालेखित. अभिगमन तिथि 2009-12-18.
  6. ↑ "LatticeMico32 Architecture". Lattice Semiconductor. मूल से 23 जून 2010 को पुरालेखित. अभिगमन तिथि 2009-12-18.
  7. ↑ "Open Source Licensing". Lattice Semiconductor. मूल से 20 जून 2010 को पुरालेखित. अभिगमन तिथि 2009-12-18.
  8. ↑ "Power ISA V2.06" (PDF). IBM. अभिगमन तिथि 2009-07-04. [मृत कड़ियाँ]
  9. ↑ http://www.ibm.com/developerworks/power/newto/#2 Archived 2012-08-29 at the वेबैक मशीन New to Cell/B.E., multicore, and Power Architecture technology
  10. ↑ http://www.sparc.org/specificationsDocuments.html# Archived 2012-02-22 at the वेबैक मशीन#ArchLic SPARC Architecture License
  11. ↑ http://www.amd.com/us-en/Processors/ProductInformation/0, 30_118_1260_1288%5E1295,00.html
  12. ↑ "संग्रहीत प्रति". मूल से 4 मई 2012 को पुरालेखित. अभिगमन तिथि 21 सितंबर 2012.
  13. ↑ Intel Itanium 2 Processor Hardware Developer's Manual. p. 14. <http://www.intel.com/design/itanium2/manuals/25110901.pdf Archived 2006-12-12 at the वेबैक मशीन> (2002) [Retrieved November 28, 2011]
  14. ↑ "संग्रहीत प्रति". मूल से 22 सितंबर 2012 को पुरालेखित. अभिगमन तिथि 21 सितंबर 2012.
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